Highly automated CMOS line

Fraunhofer EMFT is DIN EN ISO 9001 certified. This means that the workflows and procedures in our semiconductor cleanroom are clearly defined and regulated, ensuring the quality of our work and results in our research operations.

To ensure sustainable quality assurance, all parts of our institute must work together seamlessly. That is why we are constantly working to further optimize our internal processes.

Oxidation

Building up of SiO2 layers, 4 nm to 3 µm thick, through wet or dry oxidation, optionally with HCl, in temperature range of 650 °C to 1250 °C. Wafer sizes of 150 mm and 200 mm can be processed. The processing takes place in Tempress horizontal oven. Tempress AtmoScan system is available for nm thin oxide layers.

Diffusion

Introduction of dopants, activating implantations, and spreading of BPSG layers in an inert or oxidizing atmosphere in temperature range of 650 °C to 1250 °C. Wafer sizes of 150 mm and 200 mm can be processed. The processing takes place in Tempress horizontal oven.

RTP (Rapid Thermal Processing)

Producing thin oxide layers, RNO layers, activating implantations, as well as silicidation. 200 mm wafers can be processed. The processing takes place in Mattson 2900RTP equipment.

Poly- and amorphous silicon

LPCVD (Low Pressure Chemical Vapor Deposition) layer deposition of undoped polysilicon or amorphous silicon 50 nm to 3 µm thick in temperature range of 450 °C to 650 °C. Wafer sizes of 150 mm and 200 mm can be processed. The processing takes place in Tempress horizontal oven.

TEOS LPCVD-oxide

LPCVD (Low Pressure Chemical Vapor Deposition) layer deposition of undoped polysilicon or amorphous silicon 50 nm to 3 µm thick in temperature range of 450 °C to 650 °C. Wafer sizes of 150 mm and 200 mm can be processed. The processing takes place in Tempress horizontal oven.

LPCVD-nitride

LPCVD (Low Pressure Chemical Vapor Deposition) layer deposition of silicon nitride 20 nm to 250 nm thick in temperature range of 700 °C to 800 °C. Wafer sizes of 150 mm and 200 mm can be processed. The processing takes place in Tempress horizontal oven.

Doped oxides

Deposition of BSG (Boron-Silicate Glass), PSG (Phosphor Silicate Glass) and BPSG (Boron-Phosphor Silicate Glass) for thickness of 50 nm to 2 µm in temperature range of 300 °C to 460 °C. 200 mm wafers can be processed. The processing takes place in Altatech Alta-CVD.

PECVD-oxide

PECVD (Plasma-Enhanced Chemical Vapor Deposition) of USG (Undoped Silicate Glass) for thickness of 30 nm to 3 µm in temperature range of 200 °C to 480 °C. 200 mm wafers can be processed. The processing takes place in  Altatech Alta-CVD.

Ozon-TEOS SACVD

SACVD (Sub-Atmospheric Chemical Vapor Deposition) of silicon dioxide layers 100 nm to 800 nm thick in temperature range of 300 °C to 480 °C. 200 mm wafers can be processed. The processing takes place in Altatech Alta-CVD.

PECVD-nitride

PECVD (Plasma Enhanced Chemical Vapor Deposition) of nitride layers 50 nm to 800 nm thick in temperature range of 300 °C to 400 °C. 200 mm wafers can be processed. The processing takes place in AMAT P5000 CVD chambers.

PE-oxide

Plasma supported oxidation of Si with gate oxid qualität and AI for Josephon Junctions in temperature range of 300 °C to 400 °C with integrated reduction of native oxide layers. 200 mm wafers can be processed. The processing takes place in HD Dielectrics Hyperion.

Sputtering of Al, Ti, TiN, Ta

Deposition of Al, Ti, TiN and Ta in temperature range of 50 °C to 600 °C. The layer thickness can be customized according to individual needs. The layers can be combined at will. 200 mm wafers can be processed. The processing takes place in Polyteknik Flextura 200 or in Oerlikon Clusterline 200.

MOCVD for TiN and CVD for tungsten

MOCVD (Metal-Organic Chemical Vapor Deposition) of highly compliant and insitu-compressed TiN layers 8 nm to 60 nm thick in temperature range of 340 °C to 430 °C. TDMAT is used as precursor. CVD (Chemical Vapor Deposition) of highly compliant tungsten layers 100 nm to 800 nm thick in temperature range of 380 °C to 430 °C. WF6 is used as precursor. Can be combined in-situ with TiN MOCVD, including back-etching of the tungsten and TiN layers (TSV-metallization). 200 mm wafers can be processed. The processing takes place in AMAT P5000 CVD multi-chamber system.

Metal evaporation deposition

Al deposition. The layer thickness can be customized according to individual needs. 200 mm wafers can be processed. The processing takes place in a Scia system.

Spin-on and development

Solvent based i-Line-resist technology for coatings 700 nm to 12 µm thick. Before coating the wafers can be prepared with HMDS, in order to improve the adhesion of the coating on the substrate. 150 mm and 200 mm wafers can be processed. The processing takes place completely automatically in SÜSS ACS.

Spin-on and development (beginning 2026)

i-Line-resist technology for coatings 80 nm to 10 µm thick. Before coating the wafers can be prepared with HMDS, in order to improve the adhesion of the coating on the substrate. Special coatings are possible with a cartridge system. 100 mm, 150 mm and 200 mm wafers can be processed.

Stepper lithography

Exposure of photo-sensitive layers at minimal lateral resolution of 0.35 µm. Maximum size of the exposure field 20 mm to 21 mm. 200 mm wafers can be processed. The exposure is done with i-Line-stepper Canon FPA 3000 i4.

Contact and proximity lithography

Exposure of i-Line-sensitive photoresist. The required 1:1 transfer of the structure of the shadow mask can be carried out using the requested distance (proximity) or with contact. Chrome masks are used. In addition to the standard incident light microscope, IR optics can be used for aligning the mask and the substrate. Wafer sizes of 150 mm and 200 mm can be processed. The processing takes place in the contact exposure device SÜSS MICROTEC MA8Gen4 or MA200.

Double-sided exposure

Adjusted exposure of the back side of the substrate with adjustment accuracy in 2 µm range. Wafer sizes 150 mm and 200 mm can be processed. The processing takes place in the contact exposure device SÜSS MICROTEC MA8Gen4 and MA200.

Electron beam lithography

Writing of structures smaller than 10 nm. Existing GDSII and CIF files can be read by the software and consequently utilized for structuring. The structure sizes and penetration depth can be varied using different acceleration voltages of 25KV, 50KV 100KV and 200 KV. Wafer sizes of 150 mm and 200 mm can be processed. The processing takes place in JEOL JBX-8100FS.

Special processes

Lift-off processes < 1µm are possible.

Dry resist

Use of dry resist is possible.

Reactive ion etching of dielectrics, polymers

Magnetically Enhanced Reactive Ion Etching (MERIE) processes for structuring or planar etching of dielectric layers (silicon dioxide, nitride, PSG, BPSG) in a wide thickness range from 20 nm to 6 μm for structure sizes smaller than 100 nm. Automatic endpoint detection (open area greater than 2%). Wafer cooling by means of electrostatic chuck. The etch rates for oxides are in the range of 200-400 nm/min. The processable wafer size is 200 mm. Processing takes place in eMxP+ chambers from Applied Materials (AMAT Centura). In addition, a P5000 Mark 2 oxide etching chamber from Applied Materials (AMAT) is available. Processing can also be carried out in a new RIE chamber from Applied Materials (AMAT Centura).

Reactive ion etching for poly-silicon structuring

Inductively Coupled Reactive Ion Etching for structuring or planar etching of doped or undoped amorphous or polycrystalline layers as well as silicides (e.g. transistor gate stacks) in the thickness range from 20 nm to 500 nm for structure sizes smaller than 100 nm. The processable wafer size is 200 mm. Processing takes place in a poly-DPS chamber from Applied Materials (AMAT Centura).

Reactive ion etching of conductive layers (AlSi,  AlCu, Ti, TiN, W)

AlSi/TiN/Ti/AlCu/Al structures up to 0.6 µm in width at metal thickness up to 1.5 µm (depending on the structure size) are possible. Additionally RIE-tungsten etching, structured and unstructured (W-Etchback). 200 mm wafers can be processed. The processing takes place in P5000 Mark 2 from Applied Materials (AMAT Centura), in an ASP chamber (Advanced Strip and Passivation) or in the RIE chambers.

High-rate silicon etching (Bosch process)

Deep Reactive Ion-Etching (DRIE) of bulk silicon with Bosch process for aspect ratios up to 20:1. Etching of MEMS structures with low aspect ratio at silicon etching rate of 10 µm/min to 20 µm/min (depending on the structure size). Etching of TSV (Through Silicon Vias) with aspect ratios up to 20:1 at a silicon etching rate of 2 µm/min to 5 µm/min (depending on the structure size). Additionally, silicon etching with single-step-process is available. Wafers sizes of 200 mm can be processed. The processing takes place in SPTS Pegasus or in an poly-DPS chamber of Applied Materials (AMAT Centura).

KOH etching

KOH etching in a temperature-controlled wet bench. The etching temperature is 60 °C or 80 °C. Wafer sizes of 150 mm and 200 mm can be processed as individual wafers or in batches of 12.

Wafer cleaning

Cleaning of wafers using bench processes and Spray Acid Tool. Effective removal of organic and non-organic contaminations (SC1, SC2, Caro’s acid and HF-Dip). Residues of coating and polymers can be removed using acetone, isopropanol and EKC-265 in stainless steel basin with ultrasound. Wafer sizes of 150 mm and 200 mm can be processed.

Isotropic etching processes

Structuring wet chemical etching with photoresist is possible for the following layers: poly-silicon, doped and undoped oxides as well as aluminium (Alu, AlSi and AlSiCu). An unstructured wet chemical removal of the following layers is possible: poly-silicon, doped and undoped oxides, silicon-nitride, titan-nitride, titan, tungsten and aluminium as well as aluminium alloys. Wafer sizes of 150 mm and 200 mm can be processed.

Spin-etching processes

Silicon etching and stress-relief etching using a mixture of nitric acid, phosphoric acid and hydrofluoric acid. Silicon oxide etching using hydrofluoric acid. Both  processes can be used for the front as well as the backside of the wafer. Wafer sizes of 150 mm and 200 mm can be processed. The processing takes place in Spin Processor.

Implantation of argon, hydrogen, arsenic, boron, fluor, BF2 and phosphor in doses range from 1 x 1011 cm² to 1 x 1016 cm². The energy range is 5 keV to 250 keV for single charged ions. Additionally, implantation of up to three times charged ions with energies up to 750 keV is possible. Furthermore, the implantation angle of 0° to 45° as well as rotation of 0° to 360° can be realized. Wafer sizes of 100 mm, 150 mm and 200 mm can be processed. All implantations take place in VARIAN E500 medium current implanter.

Epitaxy of Si and SiGe layers

Epitaxy of silicon and silicon-germanium layers in the RP-CVD Reactor (6 Torr to Atm). A low doping with boron and phosphor is possible, as well as deposition of highly intrinsic silicon (3000 Ohm cm). Wafer sizes of 200 mm can be processed. The processing takes place in ASM Epsilon 2000.

Grinding of silicon wafers or wafer stacks from 100 µm to maximum 2000 µm thick. Special carrier technologies make grinding of topographic wafers, processing of extreme thin MEMS wafer stacks, back-side grinding of cavities, or thinning of wafers down to 30 µm possible. Wafer sizes of 150 mm and 200 mm can be processed. The processing takes place in Disco  equipment.

In-line REM, Focused Ion Beam and TOF-SIMS

In-line REM (Schottky Emitter) and Focused Ion Beam (Ga-FIB) with EDX-analysis and Gas Injection System (GIS). TOF-SIMS possible. Wafer sizes of 100 mm, 150 mm and 200 mm can be processed. The processing takes place in FEI Helios Nanolab 650.

CD in-line REM

Handling of 100 mm, 150 mm, and 200 mm wafer sizes. Additional holders for smaller sizes can be ordered as accessories (e.g., 3“, 2”, and fragments). The nominal resolution is <=0.6 nm. The sample can be tilted up to 70° and rotated 360°. Automatic scanning of critical dimensions (CD) by loading wafer maps.Processing is performed on the JEOL JSM-IT800is.

IR microscope

IR control on chip and wafer level.

Measurement of layer thickness

Automatic ellipsometric thickness measurement of thin and transparent materials. Wafer sizes of 150 mm and 200 mm can be processed. Manual IR-spectrometric thickness measurement of silicon layers thinner than 100 µm and layers permeable for infrared light. Sample sizes of 150 mm and 200 mm can be processed.

Four-point measuring device

For 150 mm and 200 mm wafers.

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