Chiplet Innovation

Future microelectronic systems will require higher levels of functionality and efficiency which cannot be managed by a single chip, even with advanced System-on-Chip (SoC) concepts. To tackle this challenge, in the chiplet concept, the IC is “broken down” into various smaller functional parts – chiplets – instead of manufacturing one large semiconductor chip and then packaging it as a single monolithic IC component. The assembly of these multiple chiplets into a complex, often three-dimensional package results in highly integrated microelectronic systems. 

Chiplets are specialists, streamlined for their respective tasks, such as data processing, I/O handling, sensing, signal processing, memory, just to mention a few. For specific functions, such as RADAR, optics, sensing etc., optimized technologies of semiconductor wafers and in different technology nodes can be used. Thus, as a mix & match construction kit the chiplets can be assembled together to form highly performant microelectronic systems, tailored to application-specific needs. The chiplet concept promises considerable gains, including higher performance and efficiency as well as reduction of power consumption and cost for all players in the microelectronics value chain.

For the users of microelectronic systems, chiplets enable fast handling of big amounts of data and higher data transfer rates for data-hungry applications, e.g. in the areas of high-performance computing, communications, automotive or medical technology.  The overall modularity and flexibility fosters fast product innovation, affordable product development and shorter time-to-market. 

For the semiconductor industry, the benefits include higher yield and lower defects due to lower complexity and smaller size of the chiplets, which reduces the manufacturing costs. The modular concept enables scalable production due to reuse of the chiplets for various applications, leading to faster return of investment. 

To the advantage of sustainability, chiplets also help to increase resource efficiency in microelectronics production. The reuse of chiplets across applications means less use of critical raw materials. Miniaturization, reduced interconnect latency and lower heat generation lead to savings in power consumption of the overall system.

For the scientific community, the variability in the chiplet implementation technologies opens up innovation opportunities in all areas of microelectronic expertise and enables fast innovation and adaptation to rapidly changing market demands. Additionally, the envisioned open ecosystem of modular components fosters networking and cooperation between all players in the industry.

Chiplet Design

The increased design complexity of a chiplet system requires specialized tools and methodologies for optimizing the single chiplets as well as guaranteeing the seamless interaction between the chiplets. The new level of heterogeneity and modularity requires highly iterative, agile design workflows.

The Fraunhofer EMFT circuit design experts are working on provisioning of IPs and chiplets for voltage references, high speed multichannel ADC, RF-systems and power management for MEMS drivers, just to mention a few chiplet building blocks being developed at our institute. Within the APECS pilot line, our circuit design team is also simplifying the design process of chiplet-based systems by provision of foundational chiplet building blocks and methods for chiplet selection.

Seamless Chiplet Integration and Connectivity Strategies

Chiplet integration and connectivity are an essential prerequisite to successful implementation of chiplet systems. The chiplets can be interconnected on dedicated substrates (e.g. Si, glass, or polymer) side-by-side (2.5D) or 3D stacked. This heterogeneous integration of various technology nodes and materials increases the complexity of the system development and manufacturing process and requires special expertise in microelectronic integration and assembly technologies.

Heterogeneous 2,5 and 3D integration for stacking ICs on top of each other on various interposer materials and connecting them with each other is a long-term expertise of the Fraunhofer EMFT scientists. Another core competence of the Fraunhofer EMFT team is the development and processing of high-resolution structures on flexible substrates as well as chip-to-foil assembly, important for precise assembly of chiplets on various types of interposers with high-density wiring. Development and implementation of technologies and methods for assembly of multi-layered heterogeneous chiplet systems on advanced substrates such as Flex-Polymer and RF-Glass interposers also belong to the Fraunhofer EMFT tasks in the APECS pilot line.

Characterization and Reliability of Emerging Chiplet Technologies 

Combining chiplets into a functional system means utilizing a large number of small, high density, high bandwith interconnects to bring together several passive and active devices, consisting of various materials, functionalities and technologies. Due to this extreme complexity and heterogeneity, more and new degradation phenomena and failures are bound to occur. Also EMC/EMI issues will become more important at lower sensitivities and increasing frequencies of the components and systems.

The Fraunhofer EMFT experts have wide-ranging expertise in test and analysis of electric components and systems and have a state-of-the-art infrastructure for ultra-precise measurements and characterization of integrated circuits and devices at their disposal. Within the APECS pilot line, the Fraunhofer EMFT team is developing new test and characterization methods e.g. for ESD-stressing and failure analysis of complex 3-dimensional systems, to guarantee the Reliability, Availability and Serviceability (RAS) of not just the single chiplets but of the whole integrated system.