Fraunhofer Institute for Electronic Microsystems and Solid State Technologies EMFTThe APECS (short for »Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems«) pilot line under the European Chips Act aligns with the European Union´s strategic goals of enhancing technological resilience, economic growth, cross-border cooperation, green manufacturing and global competitiveness. It will systematically promote a long lasting and open approach to European stakeholders (especially SMEs and start-ups) from the entire value chain, from materials to applications.
APECS Pilot Line
One pilot line, unprecented potential
APECS pilot line focal points
Striving to become the leading European platform for advanced packaging and heterogeneous integration innovation, APECS envisions a future where the European semiconductor industry is not only internationally competitive, but also a driving force behind the next generation of integrated systems.
By bringing together diverse technologies, fostering multi-level collaboration, and providing seamless access to innovative solutions, APECS aims to build a resilient and thriving community of interest that enables European companies, from Startups through SMEs to industry leaders, to play a key role in the global semiconductor market. Furthermore, as a comprehensive platform, APECS integrates an end-to-end design and pilot production capabilities, enabling innovations to progress from cutting-edge research to practical, scalable manufacturing solutions.
Heterogeneous integration
Today, the semiconductor device industry is fundamental for all modern economies. Semiconductor research and development is at the core of current technological (r)evolutions, ranging from artificial intelligence and high-performance computing, modern defense systems to robotics, power electronics, wireless communication, e-health care, quantum technologies, and more. Such future electronic systems will require more and more functions that cannot be provided by a single chip, even if advanced system-on-chip (SoC) concepts are used. Heterogeneous integration will be the next step and will go beyond current system-in-package (SiP) approaches. This concept of true heterogeneous integration is extremely important for next-generation devices based on future CMOS nodes, SiGe, SiC, III/Vs such as GaAs or GaN and all different types of microelectromechanical systems (MEMS).
Chiplets
For conventional approaches, the amount of data to be stored is too big, the data transfer rates are too low, the available computational power is limiting, and the energy consumption, as well as the heat production of general-purpose computer processing units (CPUs) are too high. In addition, the increasingly higher costs for further node miniaturization in the IC manufacturing process will also promote the interconnection of so called chiplets. This means that intellectual property (IP) blocks made in different technology nodes will be combined on an active or passive interposer to reduce cost by increasing the production yield (smaller chips) and reuse across applications. This will also touch upon environmental properties of electronics in terms of resource efficiency, critical raw materials, modularity and re-usability of design blocks.
The APECS pilot line at Fraunhofer EMFT
Fraunhofer EMFT contributes to the APECS Pilot line with its extensive competences in the areas of circuit design, heterogeneous 2.5/3D integration, and test and analysis. The Fraunhofer EMFT scientists will be working on e.g.
- Design process of foundational chiplets and sensor chiplets
- System and Technology Co-Design (STCO) for heterogeneously integrated chiplet systems, including simulation, provision of PDK and ADK
- 2.5D and 3D Chiplet integration technologies for system scale assembly for heterogeneous systems with modules and subsystem
- Characterization and test of complex chiplet architectures and RF systems
- Sensor set-up for the quantification of ESD events during the assembly process, as well as optimized test set-ups for the robustness test/qualification of chiplets
- Demonstrators for heterointegration of high performance RF chiplets in the mm-wave and sub-THz range
Coordination and Funding
The APECS pilot line is coordinated by the Fraunhofer-Gesellschaft and implemented by the Research Fab Microelectronics Germany (FMD). As a cooperation between the Fraunhofer Group for Microelectronics and the Leibniz Institutes FBH and IHP, the FMD is the central point of contact on all matters concerning applied research and development in the field of micro and nanoelectronics in Germany and Europe.
Article in »Nature«: Europe’s pilot line for advanced packaging and heterogeneous integration of electronic components and systems (APECS)
The European Chips Act of 2022 calls for European microelectronics pilot lines to develop and validate novel design and fabrication technologies for next-generation microelectronic chips. Fundamental for new electronic components and systems, advanced packaging and heterogeneous integration technologies are the focus of the APECS pilot line.