Wafer-based Superconducting Qubit Fabrication Processes

The superconducting qubit architecture is one of the leading candidates to realize general-purpose quantum computing. Fraunhofer EMFT aims to achieve scalability of superconducting qubits beyond 1000 qubits by developing foundry-like fabrication processes at 200 mm wafer scale. The focus of the fabrication processes development is on optimizing both precision and reproducibility in chip production so that these can be applied to build general quantum computers.

Fraunhofer EMFT researchers are using the unique properties of certain circuit elements made from superconducting materials at very low temperatures to realize a quantum system on a chip with multiple qubits, which can be controlled to perform quantum computations. At the same time, such quantum chip can be designed and manufactured similar to a classical IC known from the semiconductor industry.

Superconducting qubits: Towards a scalability beyond 100

To realize such superconducting quantum chips, most of today’s approaches focus on a small-scale manufacturing utilizing specialized equipment. However, towards a true scalability of this architecture beyond 100 or even 1000 qubits, our central goal at Fraunhofer EMFT is to develop foundry-style fabrication processes of superconducting qubits using industry-standard tooling and methods on a 200 mm wafer scale and in line with established contamination guidelines within CMOS manufacturing. Utilizing the institute’s professional CMOS pilot-line and drawing from decades of in-house experience in semiconductor manufacturing, our team aims to reach not only the required precision, but also the necessary reproducibility in chip fabrication to allow the scaling needed for general-purpose quantum computing.

The key parts of a superconducting qubit chip are coplanar resonators of superconducting materials and Josephson Junctions. Using an all-aluminum process, the researchers at Fraunhofer EMFT have already demonstrated T1 coherence times approaching 100 µs. For further improvement of performance, our development focuses on the following main areas:

• Optimization of the all-aluminum process in terms of quality and on-wafer as well as wafer-to-wafer uniformity
• Characterization and quality optimization of the oxide layer in the Josephson Junctions
• Quality factor optimization of coplanar waveguide resonators made from a variety of superconductors
• CMOS-compatible integration of alternative superconductors for base-layer and resonator structures (including non-CMOS materials) in the Al-based qubit processes
• CMOS-compatible qubit chip design for integration into 3D architectures with chip-to-chip bonding and/or through-silicon vias
• Room temperature pre-characterization methods for quality control and qubit performance predictions

Our process portfolio aims to cover the full range from a bare silicon wafer to a fully 3D-integrated quantum chip, accompanied by a statistical process control concept and wafer-level functional testing. At the same time, the separate process blocks are flexible enough to be integrated into third party architectures within our design rules and contamination specifications. With its focus on fabricating superconducting qubits using industry-grade tools and processing methods on 200 mm wafers within Fraunhofer EMFTS's pilot-line, the team is aiming to help lift the technology towards the required scales for practical quantum computing applications. Our  recent results have opened the door a little bit wider. 

Learn more about our latest R&D results 

We achieve the highest published energy relaxation times of over 200 µs for superconducting qubits fabricated on large wafers using industry-standard methods. To demonstrate the reliability of our results, we provide the statistics of cryogenic characterization of many qubits and show the repeatability of our fabrication processes by analyzing over 10,000 qubit Josephson junctions at room temperature. Read more here:
CMOS-Compatible, Wafer-Scale Processed Superconducting Qubits Exceeding Energy Relaxation Times of 200us

Further details on the fabrication of these chips, the yield of qubits on large wafers and the characterization of superconducting qubits at room temperature can be found here:
Advancing Superconducting Qubits: CMOS-Compatible Processing and Room Temperature Characterization for Scalable Quantum Computing beyond 2D Architectures  

We have moved from planar components to a 3D design and developed a flip-chip qubit that is specially tailored to the qubit technology of the Fraunhofer EMFT. The successful production in the Fraunhofer EMFT pilot line confirms the functionality of the design. Read more here:
A Demonstration of Multifloating Superconducting Qubits on a 3-D Flip-Chip Platform With TLS Loss Mitigation via Apertures 

Manufacturing 3D integrated superconducting qubits is challenging. We were one of the first RTOs in the world to demonstrate the fabrication of a flip-chip device on 200mm wafers while complying with CMOS manufacturing standards and contamination constraints. Read more here:
3D-Integrated Superconducting qubits: CMOS-Compatible, Wafer-Scale Processing for Flip-Chip Architectures

Leverage our offering for superconducting qubit fabrication at Fraunhofer EMFT for your specific application needs. We are eager to collaborate and innovate with you - contact us!