Wafer-based Superconducting Qubit Manufacturing Processes

Fraunhofer EMFT develops integrated quantum circuits based on superconducting materials operating at millikelvin temperatures. Leveraging established semiconductor manufacturing principles in an industry-grade 200mm pilot-line, the quantum chips can be designed and processed in a manner closely aligned with classical integrated circuit production. This creates a viable path toward scalable quantum hardware.

Superconducting qubits: Enabling scalability beyond 100 qubits

Many current superconducting qubit systems are still fabricated using small-scale, specialized laboratory processes. To enable true scalability of QPUs, Fraunhofer EMFT focuses on the development of foundry-style, CMOS-compatible fabrication workflows for superconducting qubits on 200 mm wafers. These processes follow industrial contamination control standards and are implemented within the institute’s professional industry-grade pilot production line. Building on decades of semiconductor manufacturing expertise, Fraunhofer EMFT aims to achieve both the precision and reproducibility required to support scalable QPU fabrication.

Energy relaxation times of up to 200 µs

The key circuit elements of a superconducting qubit include coplanar microwave resonators and Josephson Junctions. Using a fully aluminum-based process flow, Fraunhofer EMFT has demonstrated energy relaxation times of up to 200 µs. To further enhance performance, uniformity, and integration capability, ongoing development targets the following areas:

• Optimization of the all-aluminum process with respect to material quality, on-wafer uniformity, and wafer-to-wafer repeatability
• Characterization and optimization of the Josephson Junction oxide barrier
• Quality factor improvements of coplanar waveguide resonators across multiple superconducting materials
• CMOS-compatible integration of alternative superconductors for base layers and resonators, including selective integration of non-CMOS materials
• Qubit chip design strategies supporting 3D integration, chip-to-chip bonding, and through-silicon vias
• Room-temperature pre-characterization and metrology for accelerated feedback and performance prediction

The institute´s process toolkit spans the entire flow from bare silicon wafer to fully 3D-integrated quantum chip and is supported by statistical process control and wafer-level functional testing. At the same time, individual process modules are designed to be modular and can be integrated into customer-specific or partner architectures within established design and contamination constraints.

With it´s professional CMOS pilot line, Fraunhofer EMFT combines semiconductor manufacturing expertise with next-generation quantum device design. The result: a scalable, reliable, and industry-ready pathway toward large-scale superconducting quantum processors.

Learn more about our latest R&D results 

We achieve the highest published energy relaxation times of over 200 µs for superconducting qubits fabricated on large wafers using industry-standard methods. To demonstrate the reliability of our results, we provide the statistics of cryogenic characterization of many qubits and show the repeatability of our fabrication processes by analyzing over 10,000 qubit Josephson junctions at room temperature. Read more here:
CMOS-Compatible, Wafer-Scale Processed Superconducting Qubits Exceeding Energy Relaxation Times of 200us

Further details on the fabrication of these chips, the yield of qubits on large wafers and the characterization of superconducting qubits at room temperature can be found here:
Advancing Superconducting Qubits: CMOS-Compatible Processing and Room Temperature Characterization for Scalable Quantum Computing beyond 2D Architectures  

We have moved from planar components to a 3D design and developed a flip-chip qubit that is specially tailored to the qubit technology of the Fraunhofer EMFT. The successful production in the Fraunhofer EMFT pilot line confirms the functionality of the design. Read more here:
A Demonstration of Multifloating Superconducting Qubits on a 3-D Flip-Chip Platform With TLS Loss Mitigation via Apertures 

Manufacturing 3D integrated superconducting qubits is challenging. We were one of the first RTOs in the world to demonstrate the fabrication of a flip-chip device on 200mm wafers while complying with CMOS manufacturing standards and contamination constraints. Read more here:
3D-Integrated Superconducting qubits: CMOS-Compatible, Wafer-Scale Processing for Flip-Chip Architectures

Leverage our offering for superconducting qubit manufacturing at Fraunhofer EMFT for your specific application needs. We are eager to collaborate and innovate with you - contact us!