Rethinking Edge AI Pipelines with Spiking Neural Networks - SENNA

The vast amount of use cases for Edge AI sets a broad range of requirements on Edge AI processors. General purpose processors are not suitable for high-performance tasks and many use cases do not have the required volume to make application specific processors commercially profitable. SENNA was developed to tackle this very challenge by enabling Spiking Neural Networks (SNN) based processing for applications with ultra-low latency and low power requirements, while providing a FPGA like versatility.
SENNA is a programmable neuromorphic processor based on a mixed-signal, circuit‑switched Field‑Programmable Spiking Neuron Array (FPSNA). It natively processes spikes with fully parallel neuron updates and direct spike input/output, enabling event‑based, time‑deterministic inference at ultra‑low latency and power. SENNA was developed in close cooperation between Fraunhofer EMFT and Fraunhofer IIS. 

Conventional edge pipelines sample analog signals, buffer them, and process time‑discrete batches detached from the true signal timing. With SENNA, we rethink this flow end‑to‑end:

• Analog feature extraction in continuous time: A neuromorphic front-end at the sensor performs feature extraction directly on the analog waveform (e.g., edges, envelopes, spectral or temporal cues) without imposing rigid sampling schedules.
• Spike encoding at the boundary: Only salient features are encoded into spikes, preserving temporal structure and sparsity.
• Continuous spiking computation: SENNA’s FPSNA processes spikes as they arrive, fully in parallel and without packet routing overhead, yielding predictable, bounded, and minimal delay through the network.
• Actuation without detours: Output spikes can directly drive actuator drivers or trigger interrupt lines for supervisory processors (e.g., in robots), closing the loop with deterministic timing.

Why neuromorphic front-ends?

The overall efficiency and responsiveness of a spiking system depend critically on what the processor is asked to compute. Presenting all raw signal content to SENNA wastes energy and latency budget; instead, the front-end should:

• Extract only task-relevant features (application- and sensor-specific).
• Encode them as spikes to preserve temporal cues and sparsity.
• Match the encoding to the SNN topology so the network achieves the best power–performance trade‑off on SENNA.

Such neuromorphic front-ends are prerequisite for time-continuous processing of sensor data with extremely low latency.

Hardware–software co-design on FPSNA

Designing such front-ends is both a circuit and a system challenge. It requires co-optimizing analog feature extraction (noise, linearity, dynamic range, bandwidth), spike encoding (thresholding, adaptive gain/decay, refractory dynamics), and the downstream SNN model. We approach this as a hardware–software co-design problem, including hardware‑aware or hardware‑in‑the‑loop training and explicit end‑to‑end latency budgeting. We investigate how FPSNA resources and routing should be organized to support the SNN topologies needed for:

• Intelligent signal processing (e.g., communication PHY adaptation, beamforming primitives)
• Closed‑loop control (ultra‑low‑latency feedback loops)
• Anomaly detection (streaming change and novelty detection)
• Acoustic RADAR (ADAR) front ends (time‑of‑flight, Doppler, micro‑Doppler)

These features place SENNA directly at the interface between sensors and actuators as a continuous‑time, time‑deterministic processor. It aligns with Fraunhofer EMFT’s mission to build sensor and actuator systems for people and the environment. The low latency and high temporal resolution also dovetail with our circuit design strengths in ultrasound and RF, where timing fidelity and phase coherence are paramount. The Fraunhofer EMFT circuit design team is contributing to the development of SENNA with these activities:

•  Neuromorphic front-ends for sensors
  • Analog feature extraction close to the sensor (continuous‑time envelopes, filters, event detectors)
  • Spike encoding circuits tailored to the downstream SNN (thresholding, adaptive dynamics, dynamic range control)
  • Co-integration with sensor interfaces (including high‑voltage MEMS drivers, low‑noise analog front‑ends)

• Hardware–software co-design for SENNA
  • Joint optimization of encoding schemes, SNN topology, and FPSNA placement/routing under latency and energy budgets
  • Hardware‑aware training and hardware‑in‑the‑loop validation for robust real‑world timing and variability
• System integration at the sensor–actuator boundary
  • Deterministic sensor‑to‑actuator loops with minimal delay
  • Exploring interfaces to ultrasound and RF systems where high temporal resolution is essential
  • Interrupt and driver interfacing for embedded controllers and robotic systems

In mission-critical applications even the smallest delays can cause significant safety risks or financial damages. For example in use cases involving medical emergencies, business transactions or reliable communication, SENNA is poised to make the decisive difference in reaction time and efficiency. 

• Faster decisions at the Edge: Streaming, time‑continuous processing collapses sample–store–process stages into immediate sensor‑to‑actuator reactions.
• Energy proportionality: Spike‑driven computation and analog pre‑selection reduce unnecessary work on irrelevant signal content.
• Predictable timing: Deterministic spike routing and parallel neuron updates enable tight, verifiable end‑to‑end latency budgets.
• Cross‑domain fit: From closed‑loop control and communication PHYs to event‑based sensing and ADAR, SENNA targets domains where timing guarantees matter.