Neuromorphic Hardware for Spiking Neural Networks

Spiking neural networks only deliver their promise when the hardware underneath them is built for spikes. At Fraunhofer EMFT we develop integrated circuits and design methodologies for neuromorphic systems, from mixed-signal processors such as SENNA to application-specific spike encoding front-ends that translate physical sensor signals into meaningful spike streams.

The result is a continuous, energy-efficient processing chain from the sensor to the actuator, designed as one system rather than as separate blocks.

Circuit Design for Neuromorphic Computing at Fraunhofer EMFT

SENNA - a programmable processor for spiking neural networks

SENNA has a unique trade-off between performance and versatility due to its Field-Programmable-Spinking-Neuron-Array (FPSNA), which processes spikes directly and in parallel as they arrive. The connections between neurons are configured before operation, avoiding packet routing and memory accesses during spike propagation. This supports highly predictable timing and very low spike-in to spike-out latency.

© Fraunhofer EMFT / Ferdinand Pscheidl
Block diagram of the SENNA architecture.

The architecture combines:

mixed-signal leaky-integrate-and-fire neurons,
digitally configurable synaptic weights,
a circuit-switched and field-programmable routing fabric,
direct parallel spike interfaces,
on-chip configuration, test and recording functions,
a scalable digital-on-top design methodology.

© Fraunhofer EMFT / Ferdinand Pscheidl
Proof-of-Concept: SENNA Prelude with its 1024 Neuron FPSNA.

The architecture is developed together with Fraunhofer IIS and targets systems where time-continuous sensor signals, event-driven computation and deterministic reaction times matter more than the sheer number of neurons on a chip.

Spike encoding front-ends from physical signals to spikes

A neuromorphic processor is most effective when the information entering the system is already represented efficiently. Our spike encoding front-ends extract application-relevant features directly from sensor signals and encode them as spikes.

Instead of continuously digitising, storing and processing every sample, an event-based front-end transmits relevant changes, temporal patterns or signal features to the neural network. This reduces data volume, conversion effort and system latency.

Possible front-end functions include:

analogue feature extraction close to the sensor,
threshold- and timing-based spike encoding,
adaptive gain and dynamic-range control,
temporal filtering and envelope extraction,
event detection and feature selection,
interfaces to photodiodes, MEMS, radar, ultrasound or other sensors,
direct connection to SENNA’s parallel spike interfaces.

Challenges in neuromorphic circuit design

Neuromorphic integrated circuits require the combination of a wide range of expertise in digital and analogue circuit design flows.

Spikes as a distinct signal type

Pulse width, timing relationships and event ordering must survive process, voltage and temperature variation.

Digital-on-top with asynchronous blocks

Automated digital implementation has to meet mixed-signal neurons and asynchronous spike propagation.

Custom cells and timing-aware interfaces

Phase synchronisation, spike generation, pulse detection and clock-domain interaction need characterised custom cells.

Large heterogeneous switched fabrics

Generation, placement, routing and verification have to scale with thousands of switchboxes and memory elements.

Mixed-signal modelling for verification

Behavioural models bring analogue neurons, spike paths and digital control into one simulation before fabrication.

Neuron modelling for SNN training

Weight variation, threshold behaviour, leakage and delay are characterised and reflected in hardware-aware training.

Ultra-low-power spike encoding

Front-ends preserve the relevant information under sensor noise, dynamic range and environmental variation.

Testability, calibration and reliability

Embedded test functions, configurable spike generators and recorders make behaviour measurable across operating conditions.

Our Expertise in Neuromorphic Hardware

Fraunhofer EMFT combines circuit design, system engineering and sensor-interface expertise to develop neuromorphic hardware from concept to validated prototype.

Architecture and system co-design

We connect sensor interfaces, spike encoders, processors and actuator interfaces into end-to-end systems and derive the latency, power and bandwidth budgets for every block.

Analog, mixed-signal and digital design

Low-power analogue circuits, mixed-signal signal processing, custom digital design, memory structures and high-speed interfaces.

Design automation

Digital-on-top implementation, automated place and route, timing analysis and generation of heterogeneous routing fabrics.

Behavioural modelling and verification

Models for neurons, spike encoders and interfaces that support top-level verification, software development and hardware-aware SNN training before silicon is available.

Front-ends and sensor interfaces

Ultra-low-power front-ends with analogue feature extraction, event detection and adaptive encoding, integrated with sensor technologies.

Characterisation and optimisation

Laboratory validation that feeds measurement results back into circuit models, training methods and system architectures.