Fraunhofer Institute for Electronic Microsystems and Solid State Technologies EMFT
Fraunhofer Institute for Electronic Microsystems and Solid State Technologies EMFT

Neuromorphic computing for energy-efficient AI

Neuromorphic chips and systems process sensor data in real time

Artificial intelligence is moving from the cloud to the edge: into sensors, machines, communication systems and mobile devices. These systems analyse data locally, react within tight time limits and run on a limited energy budget. Neuromorphic computing offers an alternative to conventional sequential or batch-based edge AI pipelines. Information is represented as short events called spikes, so computation follows the relevant changes in a signal instead of every sample.

At Fraunhofer EMFT, neuromorphic computing is a strategic research area for sensor-near AI systems with low latency and low power consumption.

Neurospark PCB AISEC Development
© Fraunhofer EMFT / Bernd Müller
Exploring hardware-in-the-loop neural architecture search in our NeuroSpark project

What is neuromorphic computing?

Neuromorphic computing uses hardware and algorithms inspired by biological nervous systems. Networks of neurons exchange short binary pulses, the spikes, over weighted synaptic connections. Timing carries information, so a spike is neither conventional digital data nor an analogue waveform.

Conventional AI pipelines convert sensor signals into large volumes of digital data, store them in memory and process them in sequential or batch-based steps. That costs power and latency, especially when data first travels to a cloud service. Neuromorphic chips keep the processing where the signal appears.

Spiking neural networks are therefore promising wherever timing, energy consumption and direct interaction with sensors or actuators decide whether a system works.

From sensor signal to action

The full potential of neuromorphic computing appears when the complete processing chain is designed together. We investigate continuous pipelines with five stages.

01

Sensor interface

A sensor captures physical signals such as light, sound, current, voltage, motion or pressure.

02

Feature extraction

An analogue or mixed-signal front-end extracts relevant features directly from the sensor signal.

03

Spike encoding

The extracted information is translated into a sparse temporal spike representation.

04

Neuromorphic processing

SENNA processes the spike streams using a configured spiking neural network.

05

Output and action

Output spikes trigger control signals, actuator drivers, alarms or higher-level embedded systems.

SENNA neuromorphic processor

SENNA is a mixed-signal neuromorphic processor architecture developed jointly by Fraunhofer EMFT and Fraunhofer IIS. It is based on a Field-Programmable Spiking-Neuron Array that combines mixed-signal neurons with a digitally configurable, circuit-switched communication fabric.

SENNA is not intended to replace large cloud-AI systems. Its strength lies in fast, local and energy-efficient processing close to sensors or actuators.

Block diagram of the SENNA architecture.
© Fraunhofer EMFT / Ferdinand Pscheidl
Block diagram of the SENNA architecture.

This architecture is designed to provide

  • direct spike input and output interfaces,
  • parallel processing of spike events,
  • predictable and time-deterministic signal propagation,
  • low spike-in to spike-out latency,
  • configurable network topologies,
  • efficient implementation of small-world and recurrent SNNs,
  • compatibility with hardware-aware training and mapping tools.
How we design the hardware

Applications for neuromorphic chips

Neuromorphic computing is relevant wherever sensor data has to be processed locally, quickly and efficiently.

Adaptive communication systems

Adaptive filtering, signal classification, equalization and control functions close to the physical communication interface, under tight latency and energy budgets.

Optical communication

Hybrid optoelectronic neuromorphic systems for robust optical signal processing, interfacing with photonic integrated circuits.

SpikeHERO project ›

Event-based sensor processing

Event-based radar, lidar and other dynamic sensors generate data that suits spike-based processing, with less conventional preprocessing and buffering.

Adaptive control systems

Control loops in robotics, motor drives and industrial automation need fast and predictable responses in a compact reconfigurable architecture.

Condition monitoring and anomaly detection

Neuromorphic front-ends detect relevant changes locally, which reduces the amount of data to transmit and speeds up the response to anomalies.

Acoustic and ultrasonic sensing

Time-of-flight, Doppler and spectral information encoded as spikes for low-latency and energy-efficient sensor systems.

Neuromorphic Motor Control with SNN
© Fraunhofer EMFT
Neuromorphic Motor Control with SNN

Neuromorphic devices

Exploring future hardware concepts

Our research also covers the physical building blocks of neurons and synapses. In the European NeurONN project, Fraunhofer EMFT and its partners investigated brain-inspired architectures based on coupled oscillating elements, with vanadium-dioxide neuron devices and memristive synapses made from novel two-dimensional materials.

This complements our work on SENNA. While SENNA is a scalable programmable processor architecture, device research explores the components of future neuromorphic hardware.

NeurONN Project

Our approach

Fraunhofer EMFT combines expertise in integrated circuit design, sensor interfaces, microsystems, advanced devices, modelling, test and system integration. This interdisciplinary approach enables us to develop neuromorphic systems from the physical sensor signal to the algorithm and hardware implementation.

We work with partners from research and industry to identify applications where neuromorphic computing can provide measurable benefits in energy consumption, latency, system complexity and local data processing.

Applied projects in neuromorphic computing

Project NeurONN

Energy efficient neuromorphic computing

Explore further

Project TEMPO

Neuromorphic chips for tomorrow's AI

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Project Senna.connect

Developer kit for spiking neural networks

Explore further

Frequently asked questions

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  • Conventional networks process numerical activations in synchronous layers. Spiking neural networks exchange short binary pulses whose timing carries information, so a neuron only becomes active when an event arrives.

  • Spiking networks can be simulated on conventional processors, but the energy and latency benefits appear on hardware that processes spikes directly, such as the SENNA architecture.

  • Neuormorphic chips can be 10–100× more efficient than conventional CPUs - but only for sparse, event-driven data (e.g., sensor signals or anomaly detection). This advantage shrinks for dense data streams, and training the chips still demands significant energy.

    At Fraunhofer EMFT, we measure efficiency at the system level, not just the chip level. A neuromorphic core only delivers real savings when paired with ultra-low-power analog front-ends, adaptive power management, and reliable packaging. With this holistic integration, devices can run for months on a single battery - the true practical benchmark for edge AI.

  • Training happens offline with hardware-aware methods. Measured neuron behaviour such as threshold variation, leakage and delay is reflected in the training models before the network is mapped onto the chip.

  • The main bottlenecks are physical interconnectivity and memory integration: as neuron counts grow, the wiring and synaptic storage demand enormous chip area and energy, while analog signal degradation and fabrication variability become harder to control. Furthermore, neuromorphic architectures rely on spike-based training algorithms that are not yet mature – scaling them up often leads to unstable convergence or requires massive digital simulation, offsetting efficiency gains.

    At Fraunhofer EMFT, we tackle these barriers by focusing on heterogeneous integration and reliable microsystems. Our work on advanced packaging, power management, and failure analysis helps neuromorphic chips scale beyond single prototypes – enabling compact, energy-autonomous edge systems where the neural core works in harmony with sensors, actuators, and energy harvesting.