SpikeHERO: photonic computing combined with neuromorphic chips

Digital communication systems have to carry ever higher data rates while using less energy and reacting faster. In future fiber-to-the-edge networks the processing moves close to the point of use, where neither a large power budget nor a long latency chain is available.

SpikeHERO explores a hybrid platform that combines optical and electrical spiking neural networks: photonic integrated circuits carry the bandwidth, a neuromorphic processor provides configurable and time-deterministic spike processing, and advanced chiplet integration holds the two together.

Highlights of Spiking Hybrid Edge Computing

500 MHz

targeted spike processing rate of the redesigned SENNA, subject to validation during the project

2 domains

optical and electrical spiking neural networks in one hybrid system

0 buffers

the photocurrent-to-spike interface is designed to be memoryless and event-driven

From photocurrent to spike

The hard part of any hybrid system is the border between the two domains. In SpikeHERO the optical signal never has to become conventional digital data first.

Photonic integrated circuit

Optical signals are processed at very high bandwidth. Photodiodes generate photocurrents that represent them.

Input neurons

Our circuits turn those photocurrents directly into digital spikes and keep the timing information intact.

Electrical SNN on SENNA

The spikes are processed in parallel, with a configurable topology and deterministic propagation.

Adaptive signal processing

Filtering, classification and adaptation functions that follow changing transmission conditions.

Input neurons for photonic integrated circuits

Together with Fraunhofer IIS we develop the input-neuron concepts that join the optical and the electrical world. They are the reason the system can stay event-driven: no sampling clock, no buffer, no conversion into a data stream that would have to be stored before it is useful.

The circuit design behind this sits in our expertise for neuromorphic hardware, where we also build spike encoding front-ends for sensors.

What the input neurons do

receive photocurrents from photodiodes on the photonic chip
convert the relevant signal information into digital spikes
preserve timing information at high data rates
offer interfaces compatible with SENNA
keep conversion overhead, latency and energy low

A high-speed redesign of SENNA

The electrical processor builds on the SENNA architecture developed by Fraunhofer EMFT and Fraunhofer IIS. For SpikeHERO we redesign it for substantially higher operating speed while keeping parallel spike processing, configurable topology and deterministic propagation. Seven questions decide whether that works.

High-speed neurons

Mixed-signal neuron operation at much higher rates.

Short spike pulses

Generating and detecting pulses that stay clean at speed.

Low-latency interfaces

Spike input and output paths with minimal delay.

Timing-aware interconnect

Routing that treats timing as information, not overhead.

Power at high spike rates

Efficiency that does not collapse when the rate rises.

Modelling and verification

Behavioural models and top-level verification before fabrication.

Chiplet interconnects

Integration with high-density connections between chiplets.

How we design neuromorphic circuits ›

Photonic Computing Output

Modelling the hybrid interface

Reliable integration needs a system-level view of the signal chain. We contribute circuit models and characterisation data for the mixed-signal neuron and interface blocks, so circuit-level decisions can be judged by their impact on the complete hybrid system.

Preparing for 3D integration

Heterogeneous integration of electrical and photonic chiplets needs high-density interconnects that carry many signals while keeping parasitics and latency low. We contribute the electrical design requirements for that stack.

Fiber-to-the-edge demonstrator

The project's use case is deliberately demanding: signal processing that adapts to changing transmission conditions under strict limits for speed, latency and energy. It is the test of whether the hybrid approach holds up.

Working on optical links that need to react faster? We are interested in signal-processing problems where bandwidth, latency and energy pull in different directions. Tell us about yours.

SpikeHERO, photonic computing combined with neuromorphic chips