Project TEMPO: Power-saving chips for neuromorphic computing

Neuromorphic computing is considered a key technology for future AI applications. The sophisticated nerve network of our human brain serves as a model. A central challenge for research is the very high energy consumption of chips for the required complex processing power. Within the ECSEL project TEMPO (Technology & Hardware for Neuromorphic Computing) the German consortium with participation of Fraunhofer EMFT is working on the development and evaluation of power-saving neuromorphic computing chips.

New integrated memory technologies for the realization of analog and digital neuromorphic circuits.
© Sikov -

Artificial intelligence (AI) has made significant advancements in recent years thanks to the rapid increase in available computational power. However, increasing computational power through homogeneous integration of conventional von Neumann computing systems is not energy-efficient or practical, owing to the considerable energy consumption and the substantial increase in bandwidth needed to transfer data between huge memory and local computing units.

Innovative neural network structures and novel hardware concepts provide a promising solution: Analog/mixed-signal neuromorphic computing chips pave the way for energy-efficient and sustainable AI based on compute-in-memory (CIM) techniques. Within the ECSEL project TEMPO (Technology & Hardware for Neuromorphic Computing), Fraunhofer EMFT is working on the development and evaluation of energy-efficient neuromorphic computing chips in the 28nm technology node.

© Fraunhofer EMFT/ Bernd Müller
Deep learning algorithm verification for neuromorphic hardware implementation

Recently, researchers have begun to employ emerging non-volatile memories (eNVM) for storing the weights in artificial neural networks (ANNs) as programmable electrical properties, such as electrical conductance. Simultaneously, an analog multiply-accumulate (MAC) operation utilizes the electrical properties of eNVMs for multiplication, while accumulating currents or charges at the output. This leads to a high degree of parallelism in the multiplications and minimizes the need for data movement associated with the weights. Unfortunately, analog operation suffers from circuit nonideality, noise, and process variation, which result in limited computational precision. Improving the throughput and energy efficiency of analog neuromorphic chips while maintaining computational precision without compromising other aspects of performance presents a significant challenge.

As part of the project, Fraunhofer EMFT researchers are focusing on the development of energy-efficient analog and mixed-signal neuromorphic hardware using ferroelectric field-effect transistors (FeFET) and static random access memories (SRAM).  The primary goal is to achieve optimum computing accuracy. Thanks to the team's profound expertise in chip development and in the creation of hardware-based AI algorithms and demonstrators for image recognition, energy-efficient, application-specific neuromorphic chips for mobile and wearable sensor systems can be produced.The project is funded by the EU under funding code 826655 as part of the ECSEL initiative and by the BMBF under funding code 16ESE0407.

You might also be interested in:

IC-design and layout

Circuit Design for Neuromorphic Computing

Research Area: Neuromorphic Computing

Project: Boosting the Internet of Things' energy efficiency

Project: Energy efficient neuromorphic Computing